Equalizer with Controllably Weighted Parallel High Pass and Low Pass Filters and Receiver Including Such an Equalizer

ABSTRACT

An adjustable equalizer that includes a first branch including a low pass filter (LPF) typically having a variable gain (β), and a second branch including a high pass filter (HPF) typically having another variable gain (α). Outputs of the branches in response to an input signal are summed to produce an equalized output. The equalizer can be implemented using CMOS technology and can be capable of equalizing an input indicative of data having a maximum data rate of at least 1 Gb/s. Typically, the equalizer is embodied in a receiver for use in equalizing a signal, indicative of video or other data, that has propagated over a serial link to the receiver.

CROSS-REFERENCE TO RELATED APPLICATIONS

This is a continuation of application Ser. No. 11/796,175, filed on Apr.27, 2007, which is a divisional of application Ser. No. 10/247,675,filed on Sep. 19, 2002 (issued as U.S. Pat. No. 8,064,508), bothentitled EQUALIZER WITH CONTROLLABLY WEIGHTED PARALLEL HIGH PASS AND LOWPASS FILTERS AND RECEIVER INCLUDING SUCH AN EQUALIZER.

TECHNICAL FIELD OF THE INVENTION

The invention pertains to circuitry for equalizing signals (e.g., highfrequency signals indicative of data having data rate greater than 1Gb/s) that have been received after propagating over a link. Typically,the inventive equalization filter is implemented using CMOS technologyand is included in a receiver coupled to a serial link to receive asignal indicative of data transmitted at a high data rate (e.g., above 1Gb/s), to perform equalization needed for reliable data recovery.

BACKGROUND OF THE INVENTION

The transmission of signals indicative of data (e.g., signals indicativeof video or audio data) to a receiver over a link degrades the data, forexample by introducing time delay error (sometimes referred to asjitter) to the data. In effect, the link applies a filter (sometimesreferred to as a “cable filter”) to the signals during propagation overthe link. The cable filter can cause inter-symbol interference (ISI).

Equalization is the application of an inverted version of a cable filterto signals received after propagation over a link. The function of anequalization filter (sometimes referred to as an “equalizer”) in areceiver is to compensate for, and preferably cancel, the cable filter.Equalization at the receiver side of a link is typically needed in orderto achieve reliable data recovery when the data rate is high (greaterthan or equal to 1 Gb/s).

A typical conventional equalizer used in a receiver employs both anadjustable high pass filter (HPF) and an adjustable low pass filter(LPF). The HPF and LPF can be adjusted to vary pole and zero locationsand gain parameters thereof, in order to minimize signal degradation inthe equalized signal (i.e., to achieve the best data “eye”), and theequalized signal can then be sampled to recover the transmitted data.

When a receiver including such a conventional equalizer is implementedusing CMOS technology, adjustment of the equalizer is impractical whenthe data rate exceeds 1 Gb/s (1 Gigabit per second) because thetransconductance (gm) for the CMOS transistor circuitry is relativelysmall and any additional switch or passive element in the equalizerwould have a large adverse effect on equalizer performance. Thus mostconventional equalizers are implemented using Bipolar or Bipolar/CMOS(BiCMOS) technology which is more costly than CMOS technology. See forexample, the paper by M. H. Shakiba, entitled “A 2.5 Gb/s Adaptive CableEqualizer,” 1999 IEEE International Solid-State Circuits Conference,Paper WP 23.3, pages 396-397 and 4483.

Several proposals have been made for implementing equalizers using CMOStechnology, such as those described in U.S. Pat. No. 6,169,764, issuedJan. 2, 2001, to Babanezhad. U.S. Pat. No. 6,169,764 suggestsimplementing an equalizer as a high pass filter using“transconductance-capacitor (or gm-C) techniques,” or as a high-pass,continuous time (RMC) filter comprising differentiators that are made upof a variable resistor along with an operational amplifier and itsdifferentiating capacitor. However, the high-pass, continuous timefilters described in U.S. Pat. No. 6,169,764 are limited to applicationsin which the data rate does not exceed several hundred Megabits persecond due to inherent limitations in both the CMOS technology and thecircuit concept employed therein.

SUMMARY OF THE INVENTION

In a class of embodiments, the invention is a controllable equalizercomprising a first branch including a low pass filter (LPF) and having afirst variable gain (sometimes referred to as gain “β”), and a secondbranch including a high pass filter (HPF) and having a second variablegain (sometimes referred to as gain “α”). The outputs of the twobranches in response to an input signal are summed to produce anequalized output. The equalizer can be implemented using CMOS technologyso that the gain parameters β and α are independently controllable andthe equalizer is capable of equalizing an input signal indicative ofdata having a maximum data rate of at least 1 Gb/s. Preferably, theequalizer's transfer function has a zero whose location can becontrolled by varying one of the gain parameters (β and α) relative tothe other of the gain parameters. Preferably also, the transfer functionhas a peak-to-DC gain difference that can be controlled by varying oneof the gain parameters relative to the other of said gain parameters.Typically, the inventive equalizer is embodied in a receiver for use inequalizing a signal that is indicative of video data (or other data)having a maximum data rate of at least 1 Gb/s, and has propagated over aserial link to the receiver.

In preferred embodiments, the equalizer is implemented with currentsharing between its branches. For example, in a class of preferredembodiments implemented using CMOS technology, the HPF includes a firstdifferential pair of MOS transistors and the LPF includes a seconddifferential pair of MOS transistors. Current flows from one node intoboth differential pairs, with a first transistor of the firstdifferential pair sharing the current with a first transistor of thesecond differential pair. Current also flows from another node into bothdifferential pairs, with a second transistor of the first differentialpair sharing the current with a second transistor of the seconddifferential pair.

In preferred embodiments useful for equalizing a differential inputsignal, the equalizer includes two differential pairs of MOStransistors. A first current source determines the tail current for onedifferential pair, a second current source determines the tail currentfor the other differential pair, and the current sources areindependently controllable. Preferably, the transistors are NMOStransistors (but they can be PMOS transistors in alternativeembodiments). Preferably, impedance elements (each having impedance Z1)are coupled between the drains of the NMOS transistors and a top railmaintained at source potential during operation. A first differentialpair includes impedance elements (each having impedance Z0) and behavesas a LPF whose gain is Z1/Z0. A second differential pair includesimpedance elements (each including an element having impedance Z0 inparallel with a capacitor having capacitance C, or the equivalent) andhas the transfer function Z1/Z0·(1+s·C·Z0), where s=jω, andω=(frequency)/2π. If both Z0 and Z1 are purely resistive, the overalltransfer function of the equalizer is Z1/Z0·(β+α·(1+s·C0·Z0)), where βis a gain parameter determined by the first differential pair'scontrollable tail current and a is a gain parameter determined by thesecond differential pair's controllable tail current.

In a class of embodiments, the invention is a receiver configured toequalize a signal, indicative of video data (or other data) having amaximum data rate of at least 1 Gb/s, that has propagated over a seriallink to the receiver. For example, the receiver can include equalizersthat filter incoming signals on multiple channels of the link (e.g., theincoming signals on channels CH0, CH1, and CH2 of a TMDS link) inaccordance with the invention to compensate for the degradation thateach signal suffers during propagation (e.g., over a long cable) from atransmitter to the receiver.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a system that can embody the invention.

FIG. 2 is a block diagram of some elements of an implementation ofreceiver 2 of FIG. 1 that embodies the invention.

FIG. 3 is a block diagram of an embodiment of the inventive equalizationcircuit.

FIG. 4 is a graph in which the dashed curve, thin solid curve, and thicksolid curve respectively represent gain applied to an input voltage bythe HPF of FIG. 3 as a function of frequency of the input voltage, gainapplied to the input voltage by the LPF of FIG. 3 as a function of inputvoltage frequency, and gain applied to the input voltage by the overallFIG. 3 filter as a function of input voltage frequency, for gainparameters β and a that satisfy β>>α.

FIG. 5 is a graph in which the dashed, thin solid, and thick solidcurves respectively represent gain applied to an input voltage by theHPF of FIG. 3 as a function of frequency of the input voltage, gainapplied to the input voltage by the LPF of FIG. 3 as a function of inputvoltage frequency, and gain applied to the input voltage by the overallFIG. 3 filter as a function of input voltage frequency, in the case thatparameter β is at least substantially equal to parameter α.

FIG. 6 is a graph in which the dashed curve, thin solid curve, and thicksolid curve respectively represent gain applied to an input voltage bythe HPF of FIG. 3 as a function of frequency of the input voltage, gainapplied to the input voltage by the LPF of FIG. 3 as a function of inputvoltage frequency, and gain applied to the input voltage by the overallFIG. 3 filter as a function of input voltage frequency, for parameters βand a that satisfy α>>β.

FIG. 7 is a block diagram of a preferred implementation of theequalization circuit of FIG. 3.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

The term “transmitter” is used herein in a broad sense to denote anydevice capable of encoding data and transmitting the encoded data over alink (and optionally also performing additional functions, which caninclude encrypting the data to be transmitted and other operationsrelated to encoding, transmission, or encryption of the data). The term“receiver” is used herein in a broad sense to denote any device capableof receiving and decoding data that has been transmitted over a link(and optionally also performing additional functions, which can includedecrypting the received data and other operations related to decoding,reception, or decryption of the received data). For example, the termtransmitter can denote a transceiver that performs the functions of areceiver as well as the functions of a transmitter.

In typical embodiments, the invention is a receiver configured to becoupled to a serial link having at least one video channel. The receiverincludes equalizer circuitry for equalizing at least one signal receivedover at least one channel of the link in accordance with the invention,before extraction of data (e.g., video data) or a clock from eachequalized signal.

One conventional serial link, used primarily for high-speed transmissionof video data from a host processor (e.g., a personal computer) to amonitor, is known as a transition minimized differential signalinginterface (“TMDS” link). The characteristics of a TMDS link include thefollowing:

1. video data are encoded and then transmitted as encoded words (each8-bit word of digital video data is converted to an encoded 10-bit wordbefore transmission);

2. the encoded video data and a video clock signal are transmitted asdifferential signals (the video clock and encoded video data aretransmitted as differential signals over conductor pairs);

3. three conductor pairs are employed to transmit the encoded video, anda fourth conductor pair is employed to transmit the video clock signal(sometimes referred to herein as a pixel clock); and

4. signal transmission occurs in one direction, from a transmitter(typically associated with a desktop or portable computer, or otherhost) to a receiver (typically an element of a monitor or other displaydevice).

A use of the TMDS serial link is the “Digital Visual Interface”interface (“DVI” link) adopted by the Digital Display Working Group. ADVI link can be implemented to include two TMDS links (which share acommon conductor pair for transmitting a video clock signal) or one TMDSlink, as well as additional control lines between the transmitter andreceiver.

A class of embodiments of the invention can be implemented in a systemof a type shown in FIG. 1. The FIG. 1 system includes a source deviceincluding transmitter 1, MPEG2 decoder 13, and microcontroller 15,coupled as shown. The system also includes a sink device includingreceiver 2, EDID ROM 23, microcontroller 25, display circuitry 26, andaudio digital-to-analog converter 27, coupled as shown, and a TMDS linkbetween transmitter 1 (and microcontroller 15) and receiver 2 (and EDIDROM 23).

The TMDS link includes channels CH0, CH1, and CH2 (each implemented as aconductor pair) for transmitting encoded video and audio data, channelCHC (also implemented as a conductor pair) for transmitting a pixelclock for the video data, Display Data Channel (“DDC”) lines forbidirectional communication between the source and a monitor associatedwith the sink in accordance with the conventional Display Data Channelstandard (the Video Electronics Standard Association's “Display DataChannel Standard,” Version 2, Rev. 0, dated Apr. 9, 1996), a Hot PlugDetect line (not shown) on which the monitor transmits a signal thatenables a processor associated with the source to identify the monitor'spresence, analog lines (not shown) for transmitting analog video fromthe source to the sink, and power lines (not shown) for providing DCpower to the sink and a monitor associated with the sink. Receiver 2 isconfigured to extract a clock for the audio data from signalstransmitted over at least one channel of the TMDS link (e.g., an audioclock determined by the pixel clock and time stamp data transmitted overone or more of data transmission channels CH0, CH1, and CH2).

Decoder 13 asserts input video (“DigVideo”) to a video data processingsubsystem of transmitter 1 and asserts input audio data (“SPDIF”) and anaudio reference clock (“MCLK”) to an audio data processing subsystem oftransmitter 1. Input audio SPDIF can be indicative of two or morestreams of audio data (e.g., left and right stereo signals). EEPROM 14stores key values and identification bits for use in encryption ofcontent to be transmitted to receiver 2. In typical implementations, theencryption is in accordance with the conventional cryptographic protocolknown as the “High-bandwidth Digital Content Protection” (“HDCP”)protocol.

In the sink device, EDID ROM 23 is coupled to the TMDS link's DDCchannel and stores status and configuration bits which can be read bymicrocontroller 15 over the DDC channel. Receiver 2 also includes aninterface (not shown) for communication via the DDC channel withmicrocontroller 15. Microcontroller 25 is coupled for I2C communicationwith receiver 2.

Receiver 2 includes core processor 29 which recovers data and a pixelclock from the signals received on channels CH0, CH1, CH2, and CHC,de-serializes the recovered data, decodes the de-serialized 10-bit TMDScode words to generate 8-bit data words, identifies which of the 8-bitwords are indicative of audio data and which are indicative of videodata, routes the audio data to a pipelined audio subsystem of receiver2, and routes the video data to a pipelined video subsystem of receiver2. The audio data are decrypted and further processed in the audiosubsystem, and the video data are decrypted and further processed in thevideo subsystem.

EEPROM 24 of the sink device stores key values and identification bitsfor use in decryption of content received from transmitter 1. Typically,the decryption is accomplished in accordance with the HDCP protocol.Display circuitry 26 receives the analog and/or digital video output byreceiver 2. Audio digital-to-analog converter 27 receives the digitalaudio output by receiver 2.

The FIG. 1 system is typically configured to operate in response to apixel clock having frequency in the range from 25 MHz to 165 MHz, andtransmitter 1 is configured to transmit such a pixel clock over channelCHC. As will be explained below, if receiver 2 implements an embodimentof the inventive equalization circuitry, the FIG. 1 system can operatein response to a pixel clock having frequency greater than 1 GHz (e.g.,when the video data transmitted over the link are in HDTV format).

During typical operation of the FIG. 1 system, transmitter 1 transmitsvideo data to receiver 2 over Channels CH0, CH1, and CH2 during activevideo periods, transmits audio data (e.g., left and right stereosignals) over one or more of Channels CH0, CH1, and CH2 to receiver 2 attimes other than during the active video periods, continuously transmitsa pixel clock (e.g., determined by the rising edges of a binarywaveform) over Channel CHC, and transmits time stamp data (over one ormore of Channels CH0, CH1, and CH2) with each burst of the audio data.The time stamp data, together with the pixel clock, determine a clockfor the audio data. Core processor 29 in receiver 2 is configured toprocess the time stamp data with the pixel clock to regenerate the audioclock employed to transmit the audio data.

Receiver 2 of FIG. 1 can be configured in accordance with the inventionto include equalizer circuitry (circuits 30, 31, 32, and 37 of FIG. 2)for equalizing signals received over channels CH0, CH1, and CH2 of theTMDS link of FIG. 1 in accordance with the invention. Optionally,receiver 2 also includes equalizer circuitry for equalizing signalsreceived over other channels of the link in accordance with theinvention. As shown in FIG. 2, receiver 2 includes equalizer circuits30, 31, and 32 which respectively assert equalized signals to datarecovery and decoding subsystems 33, 34, and 35 of core processor 20. Asshown, receiver 2 also includes equalizer circuit 37 which asserts anequalized signal to clock recovery subsystem 38. The video datadetermined by the signals transmitted over channels CH0, CH1, and CH2are typically in RGB format, and the red, green, and blue pixels aredetermined by the signals transmitted on channels CH2, CH1, and CH0,respectively. Receiver 2 of FIG. 2 is preferably implemented asintegrated circuit, or portion of an integrated circuit, using CMOStechnology.

Equalizer 30 is coupled to receive a differential signal (indicative ofblue pixels and typically also audio data) that has been transmittedover the two conductors of channel CH0, and configured to performequalization on this signal and assert the resulting equalized signal (adifferential signal) to subsystem 33 of core processor 29. Equalizer 31is coupled to receive a differential signal (indicative of green pixelsand typically also audio data) that has been transmitted over the twoconductors of channel CH1, and configured to perform equalization onthis signal and assert the resulting equalized signal (a differentialsignal) to subsystem 34 of core processor 29. Equalizer 32 is coupled toreceive a differential signal (indicative of red pixels and typicallyalso audio data) that has been transmitted over the two conductors ofchannel CH2, and configured to perform equalization on this signal andassert the resulting equalized signal (a differential signal) tosubsystem 35 of core processor 29.

Equalizer 37 is coupled to receive a differential signal (indicative ofa pixel clock) that has been transmitted over the two conductors ofchannel CHC, and is configured to perform equalization on this signaland to assert the resulting equalized signal (a differential signal) toclock recovery subsystem 38 of core processor 29. Clock recoverysubsystem 38 recovers the pixel clock from the equalized signal. Invariations on the FIG. 2 receiver, equalizer 37 is omitted, and clockrecovery subsystem 38 receives a differential signal (indicative of apixel clock) that has been transmitted over channel CHC and recovers thepixel clock from this non-equalized signal.

Each of subsystems 33, 34, and 35 asserts to splitting subsystem 36 ofcore processor 29 a stream of 8-bit words, at least some of which areindicative of video data and typically including some indicative ofaudio data. Subsystem 36 distinguishes the video data from the audiodata, routes the audio data to a pipelined audio subsystem, and routesthe video data to a pipelined video subsystem for decryption and furtherprocessing.

The inventive equalizer (e.g., each of equalizers 30, 31, 32, and 37 ofFIG. 2) is implemented to perform the functions of the filter shown inFIG. 3. The FIG. 3 filter includes a first branch including a low passfilter (LPF) and a variable gain element (whose gain is β), and a secondbranch including a high pass filter (HPF) and a variable gain element(whose gain is α). The outputs of the two branches are summed to producean equalized output (Vout) in response to an input (Vin).

The transfer function of the FIG. 3 filter has a zero whose location canbe controlled by varying the gain parameters 13 and a. The FIG. 3 filtercan be implemented using CMOS technology such that the location of itstransfer function's zero (and preferably also the transfer function'speak-to-DC gain difference) can be controlled by varying one of the gainparameters β and α relative to the other of said gain parameters, andsuch that the CMOS-implementation of the filter is useful to equalize aninput signal having at least one frequency component of frequency equalto or greater than 1 GHz.

Preferably, the FIG. 3 filter is implemented with current sharingbetween the HPF and LPF branches, as is the FIG. 7 embodiment describedbelow. The FIG. 7 filter is an example of a class of equalizationfilters having the FIG. 3 design that are implemented using CMOStechnology and in which the HPF includes a first differential pair ofMOS transistors (NMOS transistors N1 and

N2) and the LPF includes a second differential pair of MOS transistors(NMOS transistors N3 and N4). In FIG. 7, current flows from one node(node A) into both differential pairs, with a first transistor of thefirst differential pair sharing the current with a first transistor ofthe second differential pair. Current also flows from another node (nodeB) of FIG. 7 into both differential pairs, with a second transistor ofthe first differential pair (another transistor of the HPF) sharing thecurrent with a second transistor of the second differential pair(another transistor of the LPF).

In general, the gain of the inventive equalization filter and thelocation of a zero of its transfer function are controlled in accordancewith the invention in a manner that allows the filter to be implementedwith CMOS technology and to be useful to equalize an input signal havingat least one frequency component of frequency equal to or greater than 1GHz (e.g., in applications in which the input signal is indicative ofdata having a maximum data rate of at least 1 Gb/s).

The effect of independent adjustment of the gain parameters β and α ofFIG. 3 will be explained with reference to the graphs of FIGS. 4, 5, and6. In FIGS. 4, 5, 6, the dashed curves represent the gain applied to aninput voltage by a typical implementation of the HPF of FIG. 3 (as afunction of frequency of the input voltage), the thin solid curvesrepresent the gain applied to the input voltage by a typicalimplementation of the LPF of FIG. 3 as a function of frequency of theinput voltage, and the thick solid curves represent the gain applied tothe input voltage by the overall FIG. 3 filter (including such a LPF andsuch an HPF) as a function of frequency of the input voltage.

As shown in FIG. 4, when the gains β and α are set such that β>>α, theLPF (whose characteristic is represented by the thin solid curve in FIG.4) has greater weight than the HPF (whose characteristic is representedby the dashed curve in FIG. 4), and the overall filter characteristic(represented by the thick curve in FIG. 4) closely follows that of theLPF.

As shown in FIG. 6, when the gains β and α are set such that α>>β, theLPF (whose characteristic is represented by the thin solid curve in FIG.6) has less weight than the HPF (whose characteristic is represented bythe dashed curve in FIG. 6), and the overall filter characteristic(represented by the thick curve in FIG. 6) closely follows that of theHPF, so that the filter's zero is located at a relatively low frequency(f2).

As shown in FIG. 5, when the gains β and α are set to be comparable, theoverall filter characteristic (represented by the thick curve in FIG. 5)is such that the filter's zero is shifted to higher frequency (f1) thanin FIG. 6. By controlling gain β relative to gain α, the location of thezero of the FIG. 3 filter can be controlled to have any of a range ofvalues.

The expressions “high pass filter” and “HPF” are used herein (includingin the claims) in a broad sense to denote a filter having a transferfunction that is flat or substantially flat below a first frequency(where the first frequency is substantially greater than zero) and whosemagnitude, at at least some frequencies above the first frequency, isgreater than at frequencies below the first frequency. Thus, one exampleof an HPF is a filter of this type having a pass band in a frequencyrange above the first frequency (i.e., its transfer function hasmagnitude in such range greater than its magnitude at frequencies belowthe first frequency) but which rolls off at frequencies above this range(e.g., a filter whose transfer function is as shown in the dashed curveof FIG. 4, 5, or 6). Another example of an HPF is a filter of this typewhose transfer function has magnitude, in a frequency range above thefirst frequency, greater than its magnitude at frequencies below thefirst frequency, but which does not roll off significantly at higherfrequencies (at least in the range in which the input signal hasfrequency components of significant amplitude).

Typically, the HPF of the inventive equalizer (shown in FIG. 3) rollsoff at high frequencies (in the GHz range), as do the HPFimplementations whose transfer functions are shown as the dashed curvesin FIGS. 4, 5, and 6. This roll off is caused by circuit parasiticcomponents and CMOS transistor limitations and cannot practically beavoided with current process technology. It is also within the scope ofthe invention to implement the HPF of FIG. 3 using CMOS technology insuch a manner as to achieve either the same or different (and preferablyless) roll off at high frequencies (greater than 1 GHz) than shown inFIGS. 4-6.

By increasing gain α relative to gain β, to move the location of theFIG. 3 filter's zero from the location (f1) shown in FIG. 5 to a lowerfrequency, the filter's peak-to-DC gain difference increases (so thatthere is more boosting at high frequencies). This tendency is consistentwith the fact that a lower frequency pole in the cable filter (thefilter that is compensated for by the equalization filter of FIG. 3)causes more severe ISI.

FIG. 7 is a block diagram of an exemplary implementation of the FIG. 3filter. The FIG. 7 circuit assumes that the input voltage is adifferential signal determined by the difference between first potential“Vin+” and second potential “Vin−,” and generates an equalized outputsignal that is a differential signal determined by the differencebetween potential “Vout+” and potential “Vout−.” In FIG. 7, two sourceregenerative NMOS differential pairs are coupled together: a first paircomprising NMOS transistors N1 and N2, impedance elements I3 and I4, andcurrent source S1 (which determines the tail current), connected asshown; and a second pair comprising NMOS transistors N3 and N4,impedance elements I5 and I6, two capacitors C0, and current source S2(which determines the tail current), connected as shown. The gates oftransistors N1 and N4 are at input potential “Vin+” and the gates oftransistors N2 and N3 are at input potential “Vin−.” The drains oftransistors N1 and N4 are at output potential “Vout−” and the drains oftransistors N2 and N3 are at output potential “Vout+.” The firstdifferential pair of FIG. 7 corresponds to the first branch (includingLPF) of the FIG. 3 circuit, and the second differential pair of FIG. 7corresponds to the second branch (including HPF) of the FIG. 3 circuit,with impedance elements I1 and 12 (and the current through elements I1and 12) shared by both branches.

Impedance element I1 (having impedance value Z1) is coupled between thedrains of transistors N1 and N4 and a top rail maintained at sourcepotential during operation, and impedance element I2 (also havingimpedance value Z1) is coupled between the drains of transistors N2 andN3 and the top rail. Each of elements I3, I4, I5, and I6 has theimpedance value Z0. In preferred implementations, each of impedanceelements I1, I2, I3, I4, I5, and I6 is purely resistive. In alternativeimplementations, one or more of the impedance elements can be bothinductive and resistive, or purely inductive.

Current sources S1 and S2 are independently controllable. The FIG. 7filter's gain parameter β (described above with reference to FIG. 3) canbe varied by adjusting current source S1, thereby controlling the tailcurrent of the first differential pair (the differential pair includingtransistors N1 and N2). The FIG. 7 filter's gain parameter a (describedabove with reference to FIG. 3) can be varied by adjusting currentsource S2, thereby controlling the tail current of the otherdifferential pair (the differential pair including transistors N3 andN4).

The first differential pair (including transistors N1 and N2) behaves asa LPF whose gain is Z1/Z0.

The second differential pair (including transistors N3 and N4) includesan impedance element (having impedance Z0) in parallel with a capacitor(having capacitance C0) between the source of transistor N3 and currentsource S2, and an identical impedance element between the source oftransistor N4 and current source S2. Thus, the second differential pairhas the transfer function Z1/Z0·(1+s·C0·Z0), where s=jω, andω=(frequency)/2π. In variations on the FIG. 7 embodiment, the elementsbetween the source of transistor N3 and current source S2 (and betweenthe source of transistor N4 and current source S2) are replaced by otherelements having the same impedance as does a capacitance C0 in parallelwith an impedance Z0.

If both Z0 and Z1 are purely resistive, the second differential pair'stransfer function has a zero at 1/(C0·Z0), and the transfer function ofthe equalizer of FIG. 7 is Z1/Z0·(β+α·(1+s·C0·Z0)) because two outputcurrents steered by the differential pairs (the current through thechannel of N1 and the current through the channel of N4) are drawn fromnode A, and two output currents steered by the differential pairs (thecurrent through the channel of N2 and the current through the channel ofN3) are drawn from node B. The current through the channel of N1 and thecurrent through the channel of N2 (produced by a first branch of theequalizer), together with the current through the channel of N3 and thecurrent through the channel of N4 (produced by a second branch of theequalizer) determine the equalized output signal (the difference betweenthe potentials Vout+ and Vout−) produced by the equalizer.

In the FIG. 7 embodiment, the control parameters a and 13 can becontrolled independently by independently adjusting current sources S1and S2 to determine the tail current for each of the differential pairs.An advantage of the FIG. 7 design is that this adjustment does notrequire any variable resistor or capacitor, since variable resistors andvariable capacitors are costly and difficult to control. Furthermore,the control path is totally isolated from high frequency signal path,resulting in no negative effect on equalizer performance.

Variations on the FIG. 7 embodiment are contemplated, includingvariations in which the impedance elements (including the capacitors)shown in FIG. 7 are replaced by different impedance elements.

If more equalization or bigger DC-to-peak gain difference is needed, onecan employ a variation on the FIG. 7 embodiment in which one stage ofthe FIG. 7 filter is cascaded (e.g., cascaded many times).

The FIG. 7 filter can be implemented to be useful to performequalization of a differential input signal indicative of data having amaximum data rate of at least 2 Gb/s when implemented by any of avariety of CMOS integrated circuit fabrication processes, including a0.35 μm process or a 0.18 μm process. In one embodiment, implementedusing a 0.35 μm process, the filter is useful to perform equalization ofa differential input signal indicative of data having a maximum datarate of at least 1.65 Gb/s.

In some variations on the FIG. 3 or FIG. 7 filter, the filter is anadaptive equalizer including a servo mechanism. For example, such aservo mechanism could vary the β and α parameters automatically to adaptthe filter for use with cables of different length.

Another aspect of the invention is a system including a transmitter, areceiver, and a serial link between the transmitter and receiver,wherein the receiver includes any embodiment of the inventive equalizer.

It should be understood that while certain forms of the invention havebeen illustrated and described herein, the invention is not to belimited to the specific embodiments described and shown or the specificmethods described. The claims that describe methods do not imply anyspecific order of steps unless explicitly described in the claimlanguage.

1. An equalizer, comprising: a first branch configured to realize a low pass filter and having a variable first gain, wherein the first branch is configured to low-pass filter an input signal and apply the first gain to the input signal; a second branch configured to realize a high pass filter and having a variable second gain, wherein the second branch is configured to high-pass filter the input signal and apply the second gain to the input signal; at least one input node, from which the input signal is asserted to the first branch and the second branch; and at least one output node, common to both the first branch and the second branch, at which the equalizer asserts an equalized signal in response to the input signal, wherein the equalizer has a transfer function having a zero whose location can be controlled by varying one of the first gain and the second gain relative to the other of said first gain and said second gain.
 2. The equalizer of claim 1, wherein the first branch and the second branch include at least some circuitry common to both said first branch and said second branch.
 3. The equalizer of claim 1, wherein the first gain and the second gain are independently controllable.
 4. The equalizer of claim 1, wherein each of the first gain and the second gain is based on at least one of a channel characteristic, a transmitter characteristic, and a receiver characteristic.
 5. The equalizer of claim 1, wherein said equalizer is implemented in a receiver to which the input signal has propagated over a link, the input signal is indicative of data, the equalized signal is indicative of the data, and the receiver includes additional circuitry coupled and configured to recover the data from the equalized signal.
 6. The equalizer of claim 1, wherein the transfer function has a peak-to-DC gain difference that can be controlled by varying one of the first gain and the second gain relative to the other of said first gain and said second gain.
 7. The equalizer of claim 1, wherein each of the input signal and the equalized signal is a differential signal, and the at least one output node is a pair of nodes at which the equalizer asserts components of the equalized signal.
 8. The equalizer of claim 1, wherein the equalizer is implemented using CMOS technology.
 9. The equalizer of claim 1, wherein the input signal is indicative of data having a maximum data rate of at least 1 Gb/s, and the equalizer is implemented using CMOS technology.
 10. The equalizer of claim 1, wherein each of the input signal and the equalized signal is a differential signal, the first branch includes a first differential pair, the second branch includes a second differential pair, the first differential pair includes a first MOS transistor and a second MOS transistor, the second differential pair includes a third MOS transistor and a fourth MOS transistor, a gate of each of the first MOS transistor and the fourth MOS transistor is coupled to receive a first component of the input signal, a gate of each of the second MOS transistor and the third MOS transistor is coupled to receive a second component of the input signal, current flows from a first current sharing node through the first MOS transistor and the fourth MOS transistor during operation of the equalizer, and current flows from a second current sharing node through the second MOS transistor and the third MOS transistor during operation of the equalizer.
 11. The equalizer of claim 10, wherein the first differential pair includes a first controllable current source coupled to sink a variable first tail current that determines the first gain, and the second differential pair includes a second controllable current source coupled to sink a variable second tail current that determines the second gain.
 12. An equalizer implemented using CMOS technology, comprising: a first branch configured to realize a low pass filter, wherein the first branch is configured to low-pass filter an input signal; a second branch configured to realize a high pass filter, wherein the second branch is configured to high-pass filter the input signal; at least one input node, from which the input signal is asserted to the first branch and the second branch; and at least one output node, common to both the first branch and the second branch, at which the equalizer asserts an equalized signal in response to the input signal.
 13. The equalizer of claim 12, wherein the first branch and the second branch include at least some circuitry common to both said first branch and said second branch.
 14. The equalizer of claim 12, wherein the first branch has a variable first gain, the first branch is configured to low-pass filter the input signal and apply the first gain to the input signal, the second branch has a variable second gain, the second branch is configured to high-pass filter the input signal and apply the second gain to the input signal, and the first gain and the second gain are independently controllable.
 15. The equalizer of claim 12, wherein the first branch is configured to low-pass filter the input signal and apply a first gain to the input signal, the second branch is configured to high-pass filter the input signal and apply a second gain to the input signal, and each of the first gain and the second gain is based on at least one of a channel characteristic, a transmitter characteristic, and a receiver characteristic.
 16. The equalizer of claim 12, wherein said equalizer is implemented in a receiver to which the input signal has propagated over a link, the input signal is indicative of data, the equalized signal is indicative of the data, and the receiver includes additional circuitry coupled and configured to recover the data from the equalized signal.
 17. The equalizer of claim 14, wherein the equalizer has a transfer function having a zero whose location can be controlled by varying one of the first gain and the second gain relative to the other of said first gain and said second gain.
 18. The equalizer of claim 17, wherein the transfer function has a peak-to-DC gain difference that can be controlled by varying one of the first gain and the second gain relative to the other of said first gain and said second gain.
 19. The equalizer of claim 12, wherein each of the input signal and the equalized signal is a differential signal, and the at least one output node is a pair of nodes at which the equalizer asserts components of the equalized signal.
 20. The equalizer of claim 12, wherein the input signal is indicative of data having a maximum data rate of at least 1 Gb/s.
 21. The equalizer of claim 12, wherein each of the input signal and the equalized signal is a differential signal, the first branch includes a first differential pair, the second branch includes a second differential pair, the first differential pair includes a first MOS transistor and a second MOS transistor, the second differential pair includes a third MOS transistor and a fourth MOS transistor, a gate of each of the first MOS transistor and the fourth MOS transistor is coupled to receive a first component of the input signal, a gate of each of the second MOS transistor and the third MOS transistor is coupled to receive a second component of the input signal, current flows from a first current sharing node through the first MOS transistor and the fourth MOS transistor during operation of the equalizer, and current flows from a second current sharing node through the second MOS transistor and the third MOS transistor during operation of the equalizer.
 22. The equalizer of claim 21, wherein the first differential pair includes a first controllable current source coupled to sink a variable first tail current that determines the first gain, and the second differential pair includes a second controllable current source coupled to sink a variable second tail current that determines the second gain.
 23. An equalizer implemented using CMOS technology, comprising: a first branch configured to realize a low pass filter; a second branch configured to realize a high pass filter; at least one input node, from which an input signal is asserted to the first branch and the second branch; and at least one output node, common to both the first branch and the second branch, at which the equalizer asserts an equalized signal in response to the input signal.
 24. The equalizer of claim 23, wherein the first branch and the second branch include at least some circuitry common to both said first branch and said second branch.
 25. The equalizer of claim 23, wherein said equalizer is implemented in a receiver to which the input signal has propagated over a link, the input signal is indicative of data, the equalized signal is indicative of the data, and the receiver includes additional circuitry coupled and configured to recover the data from the equalized signal,
 26. The equalizer of claim 23, wherein each of the input signal and the equalized signal is a differential signal, and the at least one output node is a pair of nodes at which the equalizer asserts components of the equalized signal.
 27. The equalizer of claim 23, wherein the input signal is indicative of data having a maximum data rate of at least 1 Gb/s.
 28. The equalizer of claim 23, wherein each of the input signal and the equalized signal is a differential signal, the first branch includes a first differential pair, the second branch includes a second differential pair, the first differential pair includes a first MOS transistor and a second MOS transistor, the second differential pair includes a third MOS transistor and a fourth MOS transistor, a gate of each of the first MOS transistor and the fourth MOS transistor is coupled to receive a first component of the input signal, a gate of each of the second MOS transistor and the third MOS transistor is coupled to receive a second component of the input signal, current flows from a first current sharing node through the first MOS transistor and the fourth MOS transistor during operation of the equalizer, and current flows from a second current sharing node through the second MOS transistor and the third MOS transistor during operation of the equalizer.
 29. The equalizer of claim 28, wherein the first differential pair includes a first controllable current source coupled to sink a variable first tail current that determines a variable first gain, and the second differential pair includes a second controllable current source coupled to sink a variable second tail current that determines a variable second gain.
 30. The equalizer of claim 29, wherein the equalizer has a transfer function having a zero whose location can be controlled by controlling one or both of the first controllable current source and the second controllable current source to vary one of the first tail current and the second tail current relative to the other of the first tail current and the second tail current. 